Discussion on the figures of merit of identified traps located in the Si film : surface versus volume trap densities

The aim of this work is a discussion on the figures of merit of identified traps located in the depletion zone (Si film) of advanced MOSFET devices. Two methodologies to estimate the volume trap densities are investigated, one using the relationship between the surface trap density and volume trap density and a second one based on the temperature evolution at fixed frequency of the generation-recombination plateau level associated to the same trap. By comparing the volume trap densities estimated using these two methods, the results are not agreeing with each other, suggesting that these methods can no longer be used with accuracy in multigate devices. Moreover, they may lead in certain cases to results physically not correct. Even about of the volume defects, the linear evolution between the plateau and the characteristic frequency of the generation-recombination contributions associated to the same trap give us the surface trap density without any additional assumption

An investigation on border traps in III-V MOSFETs with an In0.53Ga0.47As channel

Continuing CMOS performance scaling requires developing MOSFETs of high-mobility semiconductors and InGaAs is a strong candidate for n-channel. InGaAs MOSFETs, however, suffer from high densities of border traps, and their origin and impact on device characteristics are poorly understood at present. In this paper, the border traps in nMOSFETs with an In0.53Ga0.47As channel and Al2O3 gate oxide are investigated using the discharging-based energy profiling technique. By analyzing the trap energy distributions after charging under different gate biases, two types of border traps together with their energy distributions are identified. Their different dependences on temperature and charging time support that they have different physical origins. The impact of channel thickness on them is also discussed. Identifying and understanding these different types of border traps can assist in the future process optimization. Moreover, border trap study can yield crucial information for long-term reliability modeling and device timeto-failure projection

Two-step interconnect testing of semiconductor dies

\u3cp\u3eA method is provided for testing an interconnect (32) in a semiconductor die (30), the semiconductor die (30) having at its surface a plurality of electrical contact elements (Pad A, Pad B, Pad X, Pad Y), and comprising at least an interconnect-under-test (32) between a first electrical contact element (Pad A) and a second electrical contact element (Pad B), there being an electrical component (C) electrically coupled between the interconnect-under-test (32) and at least one third electrical contact element (Pad X, Pad Y). The method comprises testing a first signal path in the semiconductor die (30) for manufacturing defects, the first signal path comprising a first part of the interconnect-under-test (32) and a first deviation path from the interconnect-under-test (32) over the electrical component (C) to a third electrical contact element (Pad X), thus obtaining first test results; and testing a second signal path in the semiconductor die (30) for manufacturing defects, the second signal path comprising a second part of the interconnect-under-test (32) and a second deviation path from the interconnect-under-test (32) over the electrical component (C) to a third electrical contact element (Pad Y), thus obtaining second test results. The first and the second part of the interconnect-under-test together form the interconnect-under-test (32).\u3c/p\u3

Two-step interconnect testing of semiconductor dies

\u3cp\u3eThe present invention relates generally to testing of interconnects in a semiconductor die, and more particularly to testing of semiconductor chips that are three-dimensionally stacked via an interposer. In one aspect, a method for testing an interconnect in a semiconductor die comprises providing the semiconductor die, which includes a plurality of electrical contact elements formed at one or more surfaces of the semiconductor die, at least one interconnect-under-test disposed between a first electrical contact element and a second electrical contact element, and an electrical component electrically coupled between the interconnect-under-test and at least one third electrical contact element.\u3c/p\u3

Low frequency noise analysis on Si/SiGe superlattice I/O n-channel FinFETs

International audienc

Discussion on the Figures of Merit of Identified Traps Located in the Si Film: Surface Versus Volume Trap Densities

International audienc

Advanced ESD power clamp design for SOI FinFET CMOS technology

International audienceTwo novel ESD power clamp design techniques for SOI FinFET CMOS technology are reported. First, a layout improvement technique is discussed for stacked gated diodes, which reduces the required area for a given ESD robustness and at the same time reduces the on-resistance of the clamp. Secondly, circuit design techniques are used to convert a standard RC-triggered active ESD clamp into a bi-directional design, thereby alleviating the need for a separate reverse protection diode. The concepts can be applied for planar SOI as well

A Physically Unclonable Function with 0% BER Using Soft Oxide Breakdown in 40nm CMOS

© 2018 IEEE. A physically unclonable function (PUF) utilizing the randomness of soft oxide breakdown (BD) locations in MOSFETs is presented. The so-called soft-BD PUF features a self-limiting mechanism to generate one single soft-BD spot in a pair of MOSFETs; the subsequent BD location is used as the source of entropy to generate a highly stable "0" or "1" bit with an equal probability of 0.5. The soft-BD PUF comprising all the essential periphery circuits are fabricated in a 40nm CMOS process. Experiments show that the PUF has no instability in most of the operating conditions using the proposed readout scheme. The native bit error rate remains zero from V DD =0.8V to 1.5V at room temperature and from-20°C to 120°C at nominal V DD =0.9V. The throughput is shown to be at least 40 Mb/s and the PUF readout consumes only 51.8 fJ/bit. The randomness and uniqueness of the PUF are close to an ideal case, and no spatial correlation was observed.status: publishe

A Physically Unclonable Function Using Soft Oxide Breakdown Featuring 0% Native BER and 51.8fJ/bit in 40nm CMOS

status: publishe